This invention relates to the field of solid state photo-sensors and imagers referred to as Active Pixel Sensors (APS) that have active circuit elements associated with each pixel, and more specifically to Solid State Imagers that employ 4 transistor pixels with charge to voltage conversion regions that are isolated from the photodetector and correlated double sampling (CDS).
APS are solid state imagers wherein each pixel contains the typical solid state pixel elements including a photo-sensing means, reset means, a charge to voltage conversion means, a row select means, and additionally all or part of an amplifier. The photocharge collected within the pixel is converted to a corresponding voltage or current within the pixel as discussed in prior art documents such as xe2x80x9cActive Pixel Sensors: Are CCD""s Dinosaurs"ugr"xe2x80x9d, SPIE Vol. 1900-08-8194-1133 July 1993, by Eric Fossum. APS devices have been operated in a manner where each line or row of the imager is selected and then read out using a column select signal as discussed by E. Fossum in xe2x80x9cActive Pixel Sensors: Are CCD""s Dinosaurs"ugr"xe2x80x9d, SPIE Vol. 1900-08-8194-1133 July 1993 and by R. H. Nixon, S. E. Kemeny, C. O. Staller, and E. R. Fossum, in xe2x80x9c128xc3x97128 CMOS Photodiode-type Active Pixel Sensor with On-chip Timing, Control and Signal Chain Electronicsxe2x80x9d. Proceedings of the SPIE vol. 2415, Charge-Coupled Devices and Solid-State Optical Sensors V, paper 34 (1995). The selection of rows and columns within an Active Pixel Sensor is analogous to the selection of words and bits in memory devices. Here, the selection of an entire row would be analogous to selecting a word and the reading out of one of the columns of the Active Pixel Sensor would be analogous to selecting or enabling a single bit line within that word. Conventional prior art active pixel sensor devices teach architectures employing 4 transistor designs, with all 4 transistors contained within each and every pixel. The 4 transistors are typically the Transfer, Row Select, Reset, and Source Follower Amplifier transistors. While this architecture provides the advantages of yielding APS devices having the capability to easily perform CDS and provide low readout noise, these 4T pixels suffer from low fill factor. Fill factor is the percentage of pixel area that is devoted to the photosensor. Since these 4 transistors and their associated contact regions and signal buses are placed in each pixel, and since contact regions typically consume a large amount of pixel area due to the required overlap and spacings of various layers, the fill factor for the pixel is reduced because of the large area consumed that could otherwise be used for the photodetector. Connection to each of these components to the appropriate timing signal is done by metal buses that traverse the entire row of pixels. These metal buses are optically opaque and can occlude regions of the photodetector in order to fit them into the pixel pitch. This also reduces the fill factor of the pixel. Decreasing the fill factor reduces the sensitivity and saturation signal of the sensor. This adversely affects the photographic speed and dynamic range of the sensor, performance measures that are critical to obtaining good image quality.
In U.S. Pat. Nos. 6,160,281 and 6,107,655, Guidash has disclosed pixel architectures that maintain the functionality of prior art 4 transistor pixels by sharing the floating diffusion, row select transistor, reset transistor, and source follower input transistor between pixels of adjacent rows. In these architectures a single floating diffusion region is shared between 2 or 4 adjacent pixels. While this architecture provides high fill factor, it can lead to a physically larger floating diffusion region. This can cause a more non-linear charge to voltage conversion due to the voltage dependent junction capacitance of the floating diffusion being a larger percentage of the total capacitance of the charge to voltage conversion node. It can also lead to less efficient layout of the floating diffusion and reset transistors while trying to maintain identical placement of the photodetector within each pixel. Non-linear charge to voltage conversion can lead to variable color balance artifacts. Non identical placement of the photodetector within each pixel can lead to aliasing artifacts. Both of these artifacts are detrimental to image quality.
A typical prior art Photodiode APS pixel is shown in FIG. 1. The pixel in FIG. 1 is a prior art 4 transistor pixel that comprises: a photodiode (PD), and transfer transistor (TG); floating diffusion (FD); reset transistor with a reset gate (RG); row select transistor with a row select gate, (RSG); and a source follower input signal transistor (SIG). The fill factor of these prior art pixels is typically less than 25%.
Alternate pixel architectures proposed by Guidash are shown in FIGS. 2 and 3. In FIG. 2, 2 row adjacent pixels, Pixel A and Pixel B, have separate photodiodes and transfer gates, PDa, PDb, TGa and TGb respectively, but share all other components, FD, RG, RSG and SIG. In FIG. 3, 4 row and column adjacent pixels, Pixel 1a, 2a, 1b and 2b, where 1 and 2 denote the row, and a or b denote the column, have separate PD""s and TG""s, PD1a, PD2a, PD1b, PD2b, TG1a, TG2a, TG1b and TG2b, but share all other components FD, RG, RSG and SIG. In this case there are 2 transfer gate buses per row in order to prevent mixing of signal charge from adjacent columns. Although these architectures provide substantially higher fill factor or smaller pixels than the prior art pixel shown in FIG. 1, some disadvantages can ensue as discussed above. It can be seen that by having a single floating diffusion region shared by either 2 adjacent pixels as shown in FIG. 2, or by 4 adjacent pixels as shown in FIG. 3, leads to a physically larger floating diffusion than that obtained in FIG. 1. It is also evident from FIGS. 2 and 3 that the placement of the photodetector within the adjacent pixel boundaries is not identical.
It should be readily apparent that there remains a need within the art to provide an alternate pixel architecture that has a large fill factor, and the capability to perform CDS, like that of the shared amplifier pixels proposed by Guidash, that also have more linear charge to voltage conversion and with identical placement of the photodetector within each pixel.
The present invention provides a high fill factor Active Pixel Architecture with the capability to perform Correlated Double Sampling, (CDS). The functionality of a four transistor pixel is maintained, the high fill factor of a shared amplifier pixel architecture is maintained while eliminating the need for a single floating diffusion region and the attendant charge to voltage conversion non-linearity and asymmetry of adjacent photodetector placements within the array of pixels.
These and other features are provided by an image sensor having a plurality of pixels arranged in a series of row and columns comprising a semiconductor substrate having a plurality of pixels formed in rows and columns with at least two pixels that each have a charge to voltage conversion region that are spatially isolated from each other and electrically connected to the source of a single reset transistor. The pixels that share a reset transistor can also share an amplifier, and a select electrical function. The preferred embodiment envisions adjacent pixels, although, immediate adjacency is not a requirement.
The present invention provides an Active Pixel sensor with true Correlated Double Sampling (CDS). The advantage gained is high fill factor or small pixel, charge to voltage conversion linearity, and identical photodetector placement within each pixel. No disadvantages are foreseen.